Oct 17, 2018

ASR Envelope

My first envelope was a traditional ADSR envelope, adapted from Yusynth's design which uses a (7)555 timer as the core logic element. That design works great, but I originally made it only on prototyping board. Recently, in need of more envelopes, I decided to make a proper PCB layout, and revisit the envelope design in the process.

I realized that in typical uses of an ADSR envelope, I tend to set the Decay and Release controls to roughly the same value. This gives the decay and release portion of the sound the same time constant, which often sounds natural to me. I decided that it would be handy to have some envelope generators where the Decay and Release time combined in a single knob, and the result is this module which I called ASR envelope.




Merging Decay and Release into a single control greatly simplifies the logic portion of the circuit. Where the 555 timer in Yusynths design was cleverly used to create three logic states, the core logic now only needs two states which can be easily implemented with, for example, a single opamp. The three controls of the ASR envelope also fit comfortably on a 4hp eurorack panel, leaving space for a loop switch and indicator LED. The simplified circuit fits on a single PCB using all through-hole components.

Circuit description

The envelope circuit (excluding power supply and LED driver circuitry) is as follows:


The gate input is conditioned by U2A, using positive feedback (R2) to create hysteresis and form a Schmitt trigger. This turns any input gate signal into a well-defined gate with around +/- 10V levels. The rising edge of the gate is turned into a short trigger pulse (C1, R6 and D1), which is fed to U1A.

U1A is the heart of the circuit, and also uses positive feedback (R3) to form a Schmitt trigger with threshold levels (on the positive input of U1A) around +8V and -8V. In envelope mode (that is, with the loop switch S1 as shown in the schematic), it is used as a "Set-Reset flip flop" logic element. In it's default state, which we will call Reset, the STATE output of the flip flop is low (around -10V). When a trigger pulse arrives, the flip flop is Set, STATE goes high and the timing capacitor C2 is charged through D2. The charging rate is set by the Attack potentiometer RV1. The voltage on C2 is buffered by U1B, which in turn feeds the output of the module.

The output is also fed back to the negative input of U1A. When the charging curve reaches +8V, the flip-flop is Reset and STATE goes low. Now starts the discharge phase. C2 can only discharge through the Release potentiometer RV3, which sets the discharge rate, and the "precision diode" formed by U2B and D4. The precision diode arrangement compensates the diode drop of D4, such that will discharge to exactly the voltage on the positive input (pin 5) of U2B. Note that R11 and C7 are needed to stabilize the opamp which otherwise has difficulty with the large capacitive load C2.

The discharge voltage (pin 5 of U2B) depends on several factors. If the gate input is still high, we are in the Decay/Sustain phase of the cycle, and C2 will discharge to a voltage set by the Sustain potentiometer RV2 through D3. R9 is chosen so the Sustain level is 100% when RV2 is fully clockwise. If the gate is low, we are in the Release phase, and C2 will discharge to 0V, set by R12. The combination of D3, D5 and R12 forms a diode-OR or maximum value circuit: the voltage presented to U2B is the highest of the sustain voltage (through D3) or STATE (through D5), minus one diode drop. When both are negative, it is clipped to 0V by R12. Note that STATE is only positive during the Attack phase, and it's role here is to prevent discharging of C2 during Attack.

This completes the normal four-phase envelope cycle, and the system is back to it's default state with STATE low and the output at 0V. The typical envelope shape at the output is as follows, with a peak voltage around 8V:

Typical envelope shape

When the gate length is shorter than the Attack phase or the Sustain control is fully CCW, the Decay and Sustain phases are skipped and we have an AR envelope shape. The shortest possible AR envelope has an attack of about 1.5 ms, limited by R4 (which is needed to avoid burning out the logarithmic pot at the shortest settings). The decay time is similarly limited by R10.

Shortest AR envelope

Switching the loop switch S1 disables the Sustain circuit and bypasses D5. Now, the STATE signal is connected directly to both the charging and discharging side, and the circuit becomes a standard relaxation oscillator. This generates a bipolar triangle-like LFO waveform, with adjustable rise and fall rates (by Attack and Release, respectively), with output levels of approximately +/- 8V.

Typical waveform in loop mode

The complete schematic and bill of materials are available in the build documentation below, which also contains some important notes on what components to use.

Build documentation

I offer the PCB for this module for sale. The build documentation below contains everything you need to know to complete a successful module. Please read it through carefully before starting, and especially check the notes in the Bill of Materials when ordering parts.

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